The present invention relates to techniques for designing semiconductor integrated circuits and more particularly to techniques used effectively for designing routes in the semiconductor integrated circuits. Particularly, the present invention relates to techniques used effectively for designing the wiring for interconnection of components that compose an analog circuit built in a semiconductor integrated circuit.
A maze method or a channel allocating method is known as a process for determining routes in a semiconductor integrated circuit in their design. In the maze method, a label xe2x80x9c1xe2x80x9d is attached to a cell next to a particular cell (starting point) of a matrix corresponding to a line cell; a label xe2x80x9c2xe2x80x9d to a cell next to the label xe2x80x9c1xe2x80x9d, and so on. In this way, labels are sequentially attached. If a target cell is reached, the successive labels xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d . . . are traced from the beginning to thereby search for the route.
In the channel allocating method, a route is determined for each of wiring areas (channels) provided between cells. This allocating method is used widely in interconnecting of logic gates of a digital circuit. An algorithm for determining a route in the maze method/channel allocating method is disclosed, for example, in S. MUROGA, xe2x80x9cVLSI SYSTEM DESIGNxe2x80x9d, John Wiley and Sons, Inc., 1982, pp. 348-351.
The conventional route determining method is considerably effective for interconnections of logical gates in a digital circuit. To this end, various automatic routing tools (programs) have been provided. For analog circuits, the circuit, characteristics, for example, of an amplifier circuit required by its manufactured article are, however, different from those required by another article. Thus, the circuit compositions vary little by little and the routes must be determined at the respective element levels.
There are a few kinds of such automatic routing tools for analog circuits, but the analog circuits are required to exhibit desired characteristics and sufficient accuracy unlike the digital circuits where timings of signals are dominating. Therefore, the conventional automatic routing tools for the analog circuits have not sufficiently attained a reduction in the number of designs, for example, the user must specify the priority order of determining the route and an outline of the route.
It is therefore an object of the present invention to provide a route design method reduced in man-hours of design suitable for an automatic wiring design of an analog circuit.
An object of the present invention is to provide a circuit design supporting tool (program) that reduces the man-hours of design in the design of routes in an analog circuit to thereby enable the user to design the routes efficiently.
Another object of the present invention is to provide a circuit design supporting apparatus that reduces the man-hours of design in the design of routes in the analog circuit to thereby enable the user to design the routes efficiently.
Still another object of the present invention is to provide a circuit design apparatus capable of reducing the number of designs in the route design of an analog circuit and enabling the user to perform the route design.
These and other objects and novel features of the present invention will be obvious from the description of this specification and the accompanying drawings.
In order to achieve the above objects, according to one aspect of the present invention, there is provided a method or program of designing, or supporting the design of, a circuit comprising the steps of:
inputting information on a schematic representing a circuit comprising a plurality of elements and a plurality of lines that interconnects respective terminals of the plurality of elements, and a value of a power supply voltage fed through a particular one of the plurality of lines that interconnect the respective terminals of the plurality of elements;
detecting a path through which an electrical current flows in the circuit based on the inputted information on the schematic;
extracting routing nets each of which comprises a route through which an electrical current flows from among routing nets each comprising at least one line that interconnects terminals of ones of the plurality of elements in electrical connecting relationship from the inputted information on the schematic;
separating each of the extracted routing nets into a first subnet comprising a line through which an electrical current flows and a second subnet through which no electrical current flows; and
generating a constraint condition by which a route is determined for each of the first and second subnets.
According to the above method or program, each of the extracted routing nets is separated into the first subnet comprising a line through which an electrical current flows and the second subnet through which no electrical current flows, and a route is determined for each of the first and second subnets. Thus, the route is determined efficiently in the automatic routing design and the time required for the route design is reduced.
When the plurality of elements of the circuit comprise a bipolar transistor, the path detecting step or function is performed by assuming that no electrical current flows into the bipolar transistor through its base terminal. Thus, since the number of paths in the designed circuit through which the electrical currents flow is limited, the route determining algorithm is simplified to thereby determine the route efficiently. Even when such assumption is made, the determined route does not greatly affect the characteristics of the circuit because the base current is by far small compared to the collector current.
Preferably, when the first and second subnets are interconnected, the constraint condition generating step comprises generating a constraint condition that prevents a current, which would otherwise flow due to interconnection of the first and second subnets, from flowing through the second subnet. Thus, the automatic routing process performs a route design that prevents an electrical current from flowing through an undesirable path.
The schematic information inputting step or schematic information input supporting function may comprise inputting data that specifies a pair of elements among the plurality of elements of the circuit. When a required accuracy of the circuit is high, the constraint condition generating step or function may comprise interconnecting the route for the first subnet to a midpoint of the route for the second subnet that interconnects terminals of the pair of elements corresponding to each other. Thus, the automatic route design is made which prevents the voltages on the pair of elements from becoming imbalanced.
The schematic data inputting step may comprise inputting data specifying a pair of elements among the plurality of elements of the circuit and data specifying the accuracy of the pair of elements. When accuracy of the pair of elements is inputted or when the inputted accuracy is higher than a predetermined value, the constraint condition generating step may comprise connecting a midpoint of a line of the first subnet that interconnects the terminals of the pair of elements corresponding to each other with a line of another subnet. Thus, a design of a different required accuracy is possible for each pair of elements to thereby provide a circuit of increased accuracy.
The midpoint of the route for the subnet may be at equal distances from a contact point where the route is interconnected to the first terminal and another contact point where the route is interconnected to the second terminal. Thus, the automatic routing is made which prevents the voltages on a more accurate pair of elements from becoming imbalanced.
The use of the above-mentioned method or program in the route design for the analog circuit serves to decrease the man-hours of design and to do efficient designing work.
According to another aspect of the present invention, there is also provided a circuit designing apparatus comprising:
a storage device in which the circuit design supporting program of the invention is stored;
a computer for reading the program from said storage device and for executing the program;
an input device for inputting required data to said computer; and
a display device for displaying a schematic whose data is inputted by said input device.
According to such circuit designing apparatus, especially, efficient analog circuit design is achieved which is accomplished in a minimum of man-hours of design.